1. Field of the Invention
This disclosure relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device having an align key and a method of fabricating the same.
2. Description of the Related Art
A photolithography process plays an important role in manufacturing a highly-integrated semiconductor device having a stacked structure. The semiconductor device is completed through a set of photolithography processes, each of which requires a photomask to be exactly aligned on a semiconductor substrate in order to minimize misalignment between layers. To this end, in conventional photolithography and etching processes, processes of aligning the photomask and the semiconductor substrate, measuring alignment accuracy, and correcting an alignment error are performed. In order to perform such processing steps, an align key and an overlay key are disposed in predetermined areas of the semiconductor substrate.
The align key is used for aligning the photomask with a wafer before exposure during the photolithography process. The overlay key is used to measure whether a pattern on the photomask is exactly overlapped on the semiconductor substrate after exposure and development. Generally, the align key and the overlay key are formed in a structure having a step against surface within a scribe lane between main chips. For example, the align key and the overlay key are formed in a trench type structure or in a protrusion structure bulged from the semiconductor substrate. In the photolithography process, a method of making alignment and correcting thereof with the align key and the overlay key is as follows. When a light source in an alignment unit of a stepper is illuminated on the align key or the overlay key formed in the semiconductor substrate, an interference pattern is formed due to the step formed in the align key or the overlay key. By detecting light and shade of the interference pattern in a detection unit to identify a direction or a position of the semiconductor substrate, and by adjusting the semiconductor substrate or the photomask, the alignment and the correction thereof are performed.
A conventional method of forming the trench type align key is taught in Japanese Patent Publication No. 2002-134701, entitled “method of fabricating semiconductor device.”
According to the Japanese Patent Publication No. 2002-134701, a buried dielectric layer is simultaneously formed in an align key area during formation of an isolation layer in a cell area of the semiconductor substrate. Photolithography and anisotropic etching processes are then performed to selectively etch the buried dielectric layer in the align key area. As a result, an align key having a step with a predetermined depth is formed in the align key area.
Conventional flash memory devices are typically categorized as either floating gate type memory devices or floating trap type memory devices according to gate structures of unit cells. Also, the unit cells of the flash memory devices may be classified into stack gate cells or split gate cells according to the structures of the unit cells.
The conventional flash memory device having the split gate structure is taught in U.S. Pat. No. 4,783,766.
FIG. 1 is a cross-sectional view illustrating the conventional flash memory device having the split gate structure disclosed in the U.S. Pat. No. 4,783,766.
Referring to FIG. 1, an isolation layer (not shown) defining an active area 102 is disposed within a semiconductor substrate 100. A charge storage layer pattern 104 is disposed across the active area 102. The charge storage layer pattern 104 includes a tunnel dielectric layer 104a, a floating gate 104b and an inter-gate dielectric layer 104c, which are sequentially stacked. A gate dielectric layer 106 is disposed on the semiconductor substrate 100 adjacent the charge storage layer pattern 104. A control gate 108 is disposed, above the charge storage layer pattern 104 and the gate oxide layer 106.
The control gate 108 should be directly aligned with the charge storage layer pattern 104 in order to minimize alignment tolerance. However, a photolithography process for forming the control gate 108 utilizes an align key which is simultaneously formed with the isolation layer. In other words, the control gate 108 is indirectly aligned with the charge storage layer pattern 104. This may lead to misalignment between the control gate 108 and the charge storage layer pattern 104, and alignment variations may not be uniform throughout the semiconductor substrate. That is, overlap areas S between the control gates 108 and the charge storage layer patterns 104 may not be uniform throughout the semiconductor substrate. The nonuniform overlap areas S may cause nonuniform threshold voltage of programmed cells or erased cells.